Internal clocks are an integral part of any integrated circuit, and must be carefully controlled to ensure proper timing in the integrated circuit. Clock management circuits are used in an integrated circuit, such as a programmable logic device (PLD), to control timing of various clock signals of the device. Certain aspects of clock management circuits are often performed using phase-lock loop (PLL) circuits. In general, a PLL is used to synchronize the frequency and/or phase of an output clock signal to that of an input clock signal. In addition to their primary function of removing clock distribution delay, PLLs typically provide additional functionality such as frequency synthesis and phase shifting.
As shown in FIG. 1, a PLL 100 uses a voltage controlled oscillator 102, which generates a clock signal that approximates the input clock REFCLK. Control logic 104, consisting of a phase detector 106 and a filter 108, adjusts the oscillator frequency and/or phase to compensate for the clock distribution delay. The phase detector determines how much and in what direction the frequency and/or phase of the output clock signal should be adjusted relative to the input clock signal. The control logic 104 compares the input clock REFCLK to the feedback clock OSCCLK, and adjusts the oscillator clock until the rising edge of the input clock REFCLK aligns with the OSCCLK. Because a PLL generates its own clock signal by using an oscillator whose frequency of oscillation is adjusted to match a given input clock, a PLL may reduce the reference clock jitter.
A PLL could use either analog or digital circuitry. Each approach has its own advantages. An analog implementation generally produces a PLL with a finer timing resolution, and sometimes consumes less silicon area. Conventional circuits using analog controlled PLLs maintain phase alignment through feedback loops with continuous gain from the phase error signal to control the oscillator. However, analog implementations can require additional power supplies which require close control. These analog implementations also typically necessitate large loop filter elements to give low loop bandwidths needed for jitter filtering applications. A large magnitude of jitter can cause the PLL's phase detector to fail and the system to lose lock.
Conversely, digital implementations offer advantages in noise immunity, lower power consumption and better jitter performance. Digital implementations also provide the ability to stop the clock, facilitating power management. Some conventional devices use digitally controlled loops with digitally quantized gain from the phase/frequency error signal to control the oscillator. However, these structures also typically have complex digital loop filters that require significant area.
Accordingly, there is a need for a more efficient circuit for and method of generating a clock signal.